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Low-Cost 64-bit RISController w/DSP Capability
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IDT79RC4650TM
High-performance embedded 64-bit microprocessor - 64-bit integer operations - 64-bit registers - 100MHz, 133MHz, 150 MHz, 180MHz, 200MHz and 267MHz operation frequencies x High-performance DSP capability - 133.5 Million Integer Multiply-Accumulate Operations/sec @ 267 MHz x High-performance microprocessor - 133.5 M Mul-Add/second at 267MHz - 89 MFL0P/s at 250MHz - >640,000 dhrystone (2.1)/sec capability at 267MHz (352 dhrystone MIPS) x High level of integration - 64-bit, 267 MHz integer CPU - 8KB instruction cache; 8KB data cache - Integer multiply unit with 133.5M Mul-Add/sec x Low-power operation - Active power management powers-down inactive units - Standby mode x Upwardly software compatible with IDT RISController Family
Large, efficient on-chip caches - Separate 8kB Instruction and 8kB Data caches - Over 3200MB/sec bandwidth from internal caches - 2-set associative - Write-back and write-through support - Cache locking to facilitate deterministic response x Bus compatible with RC4000 family - System interface provides bandwidth up to 1000 MB/S - Direct interface to 32-bit wide or 64-bit wide systems - Synchronized to external reference clock for multi-master operation - Socket compatible with IDT RC64475 and RC64575 x Improved real-time support - Fast interrupt decode Optional cache locking x Note:"R" refers to 5V parts; "RV" refers to 3.3V parts; "RC" refers to both
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352 M IP S 64-bit C P U
64-bit register file
System C on trol C oprocessor
A d dress Tran slation/ C ache A ttribu te C ontrol
89M F L O P S Sin gle-P recision F PA
FP register file
P ip elin e C o n tro l
L oad aligner S tore A ligner Logic U nit H igh-Perform an ce In teger M u ltiply
Exception M an agem en t F u nctions
P ip e lin e C o n tro l
64-b it ad der
P ack /U n pack
F P A dd /S ub /C vt/ D iv/S qrt
FP M ultiply
C ontrol B us D ata Bu s Instru ction Bu s
Instru ction C ach e S et A (Lock able)
In stru ctio n C a che Set B 3 2 -/6 4 -b it S y n c h ro n ize d S y ste m In ter fa ce
D ata C ach e S et A (Lockable)
Data Cache Set B
The IDT logo is a registered trademark and ORION, RC4600, RC4650, RV4650, RC4700, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
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The IDT79RC4650 is a low-cost member of the IDT Microprocessor family, targeted to a variety of performance-hungry embedded applications. The RC4650 continues the IDT tradition of high-performance through high-speed pipelines, high-bandwidth caches and bus interface, 64-bit architecture, and careful attention to efficient control. The RC4650 reduces the cost of this performance relative to the RC4700 by removing functional units that are frequently unneeded for many embedded applications, such as double-precision floating point arithmetic and a TLB. The RC4650 adds features relative to the RC4700, reflective of its target applications. These features enable system cost reduction (e.g., optional 32-bit system interface) as well as higher performance for certain types of systems (e.g., cache locking, improved real-time support, integer DSP capability). The RC4650 supports a wide variety of embedded processor-based applications, such as consumer game systems, multi-media functions, internetworking equipment, switching equipment, and printing systems. Upwardly software-compatible with the RC3000 family, and bus- and upwardly software-compatible with the IDT RC4000/RC5000 family, the RC4650 will serve in many of the same applications, but, in addition supports other applications such as those requiring integer DSP functions. The RC64475 and RC64575 processors offer a direct migration path for designs based on IDT's RC4650 processors, through full pin and socket compatibility. The RC4650 brings 64-bit performance levels to lower cost systems. High performance is preserved by retaining large on-chip caches that are two-way set associative, a streamlined high-speed pipeline, highbandwidth, 64-bit execution, and facilities such as early restart for data cache misses. These techniques combine to allow the system designer 3.2GB/sec aggregate bandwidth, 1000 MB/sec bus bandwidth, 352 Dhrystone MIPS, 89 MFlops, and 133.5 M Multiply-add/second.
The RC4650 provides complete upward application-software compatibility with the IDT79RC32300TM and IDT79RC64xxxTM families of microprocessors. An array of development tools facilitates the rapid development of RC4650-based systems, enabling a wide variety of customers to take advantage of the high-performance capabilities of the processor while maintaining short time to market goals. The 64-bit computing capability of the RC4650 enables a wide variety of capabilities previously limited by the lower bandwidth and bitmanipulation rates inherent in 32-bit architectures. For example, the RC4650 can perform loads and stores from cached memory at the rate of 8-bytes every clock cycle, doubling the bandwidth of an equivalent 32bit processor. This capability, coupled with the high clock rate for the RC4650 pipeline, enables new levels of performance to be obtained from embedded systems. This data sheet provides an overview of the features and architecture of the RC4650 CPU. A more detailed description of the processor is available in the IDT79RC4650 Processor Hardware User's Manual, available from IDT. Further information on development support, applications notes, and complementary products are also available from your local IDT sales representative.
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The RC4650 family brings a high-level of integration designed for high-performance computing. The key elements of the RC4650 are briefly described below. A more detailed description of each of these subsystems is available in the User's Manual. 3LSHOLQH The RC4650 uses a 5-stage pipeline similar to the IDT79RC3000 and the IDT79RC4700. The simplicity of this pipeline allows the RC4650 to be lower cost and lower power than super-scalar or super-pipelined processors. Unlike superscalar processors, applications that have large data dependencies or that require a great deal of load/stores can still achieve performance close to the peak performance of the processor.
General Purpose Registers 63 0 r1 r2 * * * * r29 0
Multiply/Divide Registers 63 HI (Accumulate HI) 63 LO (Accumulate LO) 0 0
Program Counter 63 0 Figure 1 CPU Registers 32 310 PC
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,QWHJHU#([HFXWLRQ#(QJLQH The RC4650 implements the MIPS-III Instruction Set Architecture and is upwardly compatible with applications that run on the earlier generation parts. The RC4650 includes the same additions to the instruction set found in the RC4700 family of microprocessors, targeted at improving performance and capability while maintaining binary compatibility with earlier RC3000 processors. The extensions result in better code density, greater multi-processing support, improved performance for commonly used code sequences in operating system kernels, and faster execution of floating-point intensive applications. All resource dependencies are made transparent to the programmer, insuring transportability among implementations of the MIPS instruction set architecture. In addition, MIPS-III specifies new instructions defined to take advantage of the 64-bit architecture of the processor. Finally, the RC4650 also implements additional instructions, which are considered extensions to the MIPS-III architecture. These instructions improve the multiply and multiply-add throughput of the CPU, making it well suited to a wide variety of imaging and DSP applications. These extensions, which use opcodes allocated by MIPS Technologies for this purpose, are supported by a wide variety of development tools. The MIPS integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add, sub) and autonomous multiply/divide unit. The 64-bit register resources include: 32 generalpurpose orthogonal integer registers, the HI/LO result registers for the integer multiply/divide unit, and the program counter. In addition, the onchip floating-point co-processor adds 32 floating-point registers, and a floating-point control/status register. 5HJLVWHU#)LOH The RC4650 has thirty-two general-purpose 64-bit registers. These registers are used for scalar integer operations and address calculation. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. Figure 1 illustrates the RC4650 Register File. $/8 The RC4650 ALU consists of the integer adder and logic unit. The adder performs address calculations in addition to arithmetic operations, and the logic unit performs all logical and shift operations. Each of these units is highly optimized and can perform an operation in a single pipeline cycle. ,QWHJHU#0XOWLSO\2'LYLGH The RC4650 uses a dedicated integer multiply/divide unit, optimized for high-speed multiply and multiply-accumulate operation. Table 1 shows the performance, expressed in terms of pipeline clocks, achieved by the RC4650 integer multiply unit.
2SFRGH MULT/U, MAD/U
2SHUDQG# 6L]H 16 bit 32 bit
/DWHQF\ 3 4 3 4 6 36 68
5HSHDW 2 3 2 3 5 36 68
6WDOO 0 0 1 2 0 0 0
MUL
16 bit 32 bit
DMULT, DMULTU DIV, DIVU DDIV, DDIVU
any any any
Table 1 RC4650 Integer Multiply Operation
The MIPS-III architecture defines that the results of a multiply or divide operation are placed in the HI and LO registers. The values can then be transferred to the general purpose register file using the MFHI/ MFLO instructions. The RC4650 adds a new multiply instruction, "MUL", which can specify that the multiply results bypass the "Lo" register and are placed immediately in the primary register file. By avoiding the explicit "Movefrom-Lo" instruction required when using "Lo", throughput of multiplyintensive operations is increased. An additional enhancement offered by the RC4650 is an atomic "multiply-add" operation, MAD, used to perform multiply-accumulate operations. This instruction multiplies two numbers and adds the product to the current contents of the HI and LO registers. This operation is used in numerous DSP algorithms, and allows the RC4650 to cost reduce systems requiring a mix of DSP and control functions. Finally, aggressive implementation techniques feature low latency for these operations along with pipelining to allow new operations to be issued before a previous one has fully completed. Table 1 also shows the repeat rate (peak issue rate), latency, and number of processor stalls required for the various operations. The RC4650 performs automatic operand size detection to determine the size of the operand, and implements hardware interlocks to prevent overrun, allowing this high-performance to be achieved with simple programming. )ORDWLQJ03RLQW#&R03URFHVVRU The RC4650 incorporates an entire single-precision floating-point coprocessor on chip, including a floating-point register file and execution units. The floating-point co-processor forms a "seamless" interface with the integer unit, decoding and executing instructions in parallel with the integer unit. The RC4650's floating-point unit directly implements single-precision floating-point operations. This enables the RC4650 to perform functions such as graphics rendering, without requiring extensive die are or power consumption. The RC4650 does not directly implement the double-precision operations found in the RC64475. However, to maintain software compatibility,
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the RC4650 will signal a trap when a double-precision operation is initiated, allowing the requested function to be emulated in software. Alternatively, the system architect could use a software library emulation of double-precision functions, selected at compile time, to eliminate the overhead associated with trap and emulation. )ORDWLQJ03RLQW#8QLWV The RC4650 floating-point execution units perform single precision arithmetic, as specified in the IEEE Standard 754. The execution unit is broken into a separate multiply unit and a combined add/convert/divide/ square root unit. Overlap of multiplies and add/subtract is supported. The multiplier is partially pipelined, allowing a new multiply to begin every 6 cycles. As in the IDT79RC64475, the RC4650 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in mission-critical environments, such as ADA, and highly desirable for debugging in any environment. The floating-point unit's operation set includes floating-point add, subtract, multiply, divide, square root, conversion between fixed-point and floating-point format, conversion among floating-point formats, and floating-point compare.These operations comply with IEEE Standard 754. Double precision operations are not directly supported; attempts to execute double-precision floating point operations, or refer directly to double-precision registers, result in the RC4650 signalling a "trap" to the CPU, enabling emulation of the requested function. Table 2 gives the latencies of some of the floating-point instructions in internal processor cycles.
2SHUDWLRQ ADD SUB MUL DIV SQRT CMP FIX FLOAT ABS MOV NEG LWC1 SWC1 ,QVWUXFWLRQ#/DWHQF\ 4 4 8 32 31 3 4 6 1 1 1 2 1 Table 2 Floating-Point Operation
)ORDWLQJ03RLQW#*HQHUDO#5HJLVWHU#)LOH The floating-point register file is made up of thirty-two 32-bit registers. These registers are used as source or target registers for the single-precision operations. References to these registers as 64-bit registers (as supported in the RC64475) will cause a trap to be signalled. The floating-point control register space contains two registers; one for determining configuration and revision information for the coprocessor and one for control and status information. These are primarily involved with diagnostic software, exception handling, state saving and restoring, and control of rounding modes. 6\VWHP#&RQWURO#&R03URFHVVRU#+&33, The system control co-processor in the MIPS architecture is responsible for the virtual to physical address translation and cache protocols, the exception control system, and the diagnostics capability of the processor. In the MIPS architecture, the system control co-processor (and thus the kernel software) is implementation dependent. In the RC4650, significant changes in CP0--relative to the RC4700--have been implemented. These changes are designed to simplify memory management, facilitate debug, and speed real-time processing. 6\VWHP#&RQWURO#&R03URFHVVRU#5HJLVWHUV The RC4650 incorporates all system control co-processor (CP0) registers on-chip. These registers provide the path through which the virtual memory system's address translation is controlled, exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). In addition, the RC4650 includes registers to implement a real-time cycle counting facility, which aids in cache diagnostic testing, assists in data error detection, and facilitates software debug. Alternatively, this timer can be used as the operating system reference timer, and can signal a periodic interrupt. Table 3 shows the CP0 registers of the RC4650.
1XPEHU 0 1 2 3 4-7, 10, 2025, 29, 31 8 9 11 12 13 1DPH IBase IBound DBase DBound -- BadVAddr Count Compare Status Cause )XQFWLRQ Instruction address space base Instruction address space bound Data address space base Data address space bound Not used Virtual address on address exceptions Counts every other cycle Generate interrupt when Count = Compare Miscellaneous control/status Exception/Interrupt information
Table 3 RC4650 CPO Registers (Page 1 of 2)
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IDT79RC4650TM 1XPEHU 14 15 16 17 18 19 26 27 28 30 1DPH EPC PRId Config CAlg IWatch DWatch ECC CacheErr TagLo ErrorEPC Exception PC Processor ID Cache and system attributes Cache attributes for the eight 512MB regions of the virtual address space Instruction breakpoint virtual address Data breakpoint virtual address Used in cache diagnostics Cache diagnostics Cache index CacheError exception PC 0x80000000 0x7FFFFFF 0xA0000000 0x9FFFFFFF Cached kernel physical address space (kseg0) Unmapped, 0.5GB 0xC0000000 0xBFFFFFFF Uncached kernel physical address space (kseg1) Unmapped, 0.5GB 0xFFFFFFFF Kernel virtual address space (kseg2) Unmapped, 1.0 GB )XQFWLRQ
Kernel mode addresses do not use the base-bounds registers, but rather undergo a fixed virtual-to-physical address translation.
Table 3 RC4650 CPO Registers (Page 2 of 2)
2SHUDWLRQ#0RGHV The RC4650 supports two modes of operation: user mode and kernel mode. Kernel mode operation is typically used for exception handling and operating system kernel functions, including CP0 management and access to IO devices. In kernel mode, software has access to the entire address space and all of the co-processor 0 registers, and can select whether to enable co-processor 1 accesses. The processor enters kernel mode at reset, and whenever an exception is recognized. User mode is typically used for applications programs. User mode accesses are limited to a subset of the virtual address space and can be inhibited from accessing CP0 functions 9LUWXDO0WR03K\VLFDO#$GGUHVV#0DSSLQJ The 4GB virtual address space of the RC4650 is shown in Figure 2. The 4 GB address space is divided into addresses accessible in either kernel or user mode (kuseg), and addresses only accessible in kernel mode (kseg2:0). The RC4650 supports the use of multiple user tasks sharing common virtual addresses, but mapped to separate physical addresses. This facility is implemented via the "base-bounds" registers contained in CP0. When a user virtual address is asserted (load, store, or instruction fetch), the RC4650 compares the virtual address with the contents of the appropriate "bounds" register (instruction or data). If the virtual address is "in bounds", the value of the corresponding "base" register is added to the virtual address to form the physical address for that reference. If the address is not within bounds, an exception is signalled. This facility enables multiple user processes in a single physical memory without the use of a TLB. This type of operation is further supported by a number of development tools for the RC4650, including real-time operating systems and "position independent code."
User virtual address space (useg) Mapped, 2.0GB
0x00000000 Figure 2 Kernel/User Mode Virtual Addressing (32-bit mode)
'HEXJ#6XSSRUW To facilitate software debug, the RC4650 adds a pair of "watch" registers to CP0. When enabled, these registers will cause the CPU to take an exception when a "watched" address is appropriately accessed. ,QWHUUXSW#9HFWRU The RC4650 also adds the capability to speed interrupt exception decoding. Unlike the RC4700, which utilizes a single common exception vector for all exception types (including interrupts), the RC4650 allows kernel software to enable a separate interrupt exception vector. When enabled, this vector location speeds interrupt processing by allowing software to avoid decoding interrupts from general purpose exceptions. &DFKH#0HPRU\ To keep the RC4650's high-performance pipeline full and operating efficiently, the RC4650 incorporates on-chip instruction and data caches that can each be accessed in a single processor cycle. Each cache has its own 64-bit data path and can be accessed in parallel. The cache subsystem provides the integer and floating-point units with an aggregate bandwidth of over 3200 MB per second at a pipeline clock frequency of 267MHz. The cache subsystem is similar in construction to that found in the RC4700, although some changes have been implemented. Table 4 is an overview of the caches found on the RC4650.
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,QVWUXFWLRQ#&DFKH The RC4650 incorporates a two-way set associative on-chip instruction cache. This virtually indexed, physically tagged cache is 8KB in size and is parity protected. Because the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, thus further increasing performance by allowing these two operations to occur simultaneously. The tag holds a 20-bit physical address and valid bit, and is parity protected. The instruction cache is 64-bits wide, and can be refilled or accessed in a single processor cycle. Instruction fetches require only 32 bits per cycle, for a peak instruction bandwidth of 1068MB/sec at 267MHz. Sequential accesses take advantage of the 64-bit fetch to reduce power dissipation, and cache miss refill, can write 64 bits-per-cycle to minimize the cache miss penalty. The line size is eight instructions (32 bytes) to maximize performance. In addition, the contents of one set of the instruction cache (set "A") can be "locked" by setting a bit in a CP0 register. Locking the set prevents its contents from being overwritten by a subsequent cache miss; refill occurs then only into "set B". This operation effectively "locks" time-critical code into one 4kB set, while allowing the other set to service other instruction streams in a normal fashion. Thus, the benefits of cached performance are achieved, while deterministic real-time response is preserved. 'DWD#&DFKH For fast, single cycle data access, the RC4650 includes an 8KB onchip data cache that is two-way set associative with a fixed 32-byte (eight words) line size. Table 4 lists the RC4650 cache attributes.
&KDUDFWHULVWLFV Size Organization Line size Index Tag Write policy Line transfer order ,QVWUXFWLRQ 8KB 2-way set associative 32B vAddr11..0 pAddr31..12 n.a. read sub-block order write sequential Miss restart after transfer of Parity Cache locking entire line per-word set A 8KB 2-way set associative 32B vAddr11..0 pAddr31..12 writeback /writethru read sub-block order write sequential first word 'DWD
The data cache is protected with byte parity and its tag is protected with a single parity bit. It is virtually indexed and physically tagged to allow simultaneous address translation and data cache access The normal write policy is writeback, which means that a store to a cache line does not immediately cause memory to be updated. This increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can however select writethrough for certain address ranges, using the CAlg register in CP0. Cache protocols supported for the data cache are: Uncached. Addresses in a memory area indicated as uncached will not be read from the cache. Stores to such addresses will be written directly to main memory, without changing cache contents. x Writeback. Loads and instruction fetches will first search the cache, reading main memory only if the desired data is not cache resident. On data store operations, the cache is first searched to see if the target address is cache resident. If it is resident, the cache contents will be updated, and the cache line marked for later writeback. If the cache lookup misses, the target line is first brought into the cache before the cache is updated. x Write-through with write allocate. Loads and instruction fetches will first search the cache, reading main memory only if the desired data is not cache resident. On data store operations, the cache is first searched to see if the target address is cache resident. If it is resident, the cache contents will be updated and main memory will also be written; the state of the "writeback" bit of the cache line will be unchanged. If the cache lookup misses, the target line is first brought into the cache before the cache is updated. x Write-through without write-allocate. Loads and instruction fetches will first search the cache, reading main memory only if the desired data is not cache resident. On data store operations, the cache is first searched to see if the target address is cache resident. If it is resident, the cache contents will be updated, and the cache line marked for later writeback. If the cache lookup misses, then only main memory is written. Associated with the Data Cache is the store buffer. When the RC4650 executes a Store instruction, this single-entry buffer gets written with the store data while the tag comparison is performed. If the tag matches, then the data is written into the Data Cache in the next cycle that the Data Cache is not accessed (the next non-load cycle). The store buffer allows the RC4650 to execute a store every processor cycle and to perform back-to-back stores without penalty. :ULWH#%XIIHU
per-byte set A
Table 4 RC4650 Cache Attributes
Writes to external memory, whether cache miss writebacks or stores to uncached or write-through addresses, use the on-chip write buffer. The write buffer holds up to four address and data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory update.
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6\VWHP#,QWHUIDFH The RC4650 supports a 64-bit system interface that is bus compatible with the RC4700 system interface. In addition, the RC4650 supports a 32-bit system interface mode, allowing the CPU to interface directly with a lower cost memory system. The RC64475 supports a 64-bit system interface that is bus compatible with the RC4650 system interface. The interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit command bus protected with parity. In addition, there are 8 handshake signals and 6 interrupt inputs. The interface has a simple timing specification and is capable of transferring data between the processor and memory at a peak rate of 1000MB/sec. Figure 3 shows a typical system using the RC4650. In this example two banks of DRAMs are used to supply and accept data with a DDxxDD data pattern. The RC4650 clocking interface allows the CPU to be easily mated with external reference clocks. The CPU input clock is the bus reference clock, and can be between 50 and 125MHz (somewhat dependent on maximum pipeline speed for the CPU). An on-chip phase-locked-loop generates the pipeline clock from the system interface clock by multiplying it up an amount selected at system reset. Supported multipliers are values 2 through 8 inclusive, allowing systems to implement pipeline clocks at significantly higher frequency than the system interface clock.
6\VWHP#$GGUHVV2'DWD#%XV The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RC4650 and the rest of the system. It is protected with an 8-bit parity check bus, SysADC. When initialized for 32-bit operation, SysAD can be viewed as a 32-bit multiplexed bus, with 4 parity check bits. The system interface is configurable to allow easier interfacing to memory and I/O systems of varying frequencies. The bus frequency and reference timing of the RC4650 are taken from the input clock. The rate at which the CPU transmits data to the system interface is programmable via boot time mode control bits. The rate at which the processor receives data is fully controlled by the external device. Therefore, either a low cost interface requiring no read or write buffering or a faster, high performance interface can be designed to communicate with the RC4650. Again, the system designer has the flexibility to make these price/performance trade-offs. 6\VWHP#&RPPDQG#%XV The RC4650 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates whether the SysAD bus carries an address or data. If the SysAD carries an address, then the SysCmd bus also indicates what type of transaction is to take place (for example, a read or write). If the SysAD carries data, then the SysCmd bus also gives information about the data (for example, this is the last data word transmitted, or the cache state of this data line is clean exclusive). The SysCmd bus is bidirectional to support both processor requests and external requests to the RC4650. Processor requests are initiated by the RC4650 and responded to by an external device. External requests are issued by an external device and require the RC4650 to respond.
Address Boot ROM DRAM (80ns)
Control
SCSI
ENET
32 or 64
32 or 64
Memory I/O Controller
RC4650
9 2 11
Figure 3 Typical RC4650 System Architecture
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The RC4650 supports single datum (one to eight byte) and 8-word block transfers on the SysAD bus. In the case of a single-datum transfer, the low-order 3 address bits gives the byte address of the transfer, and the SysCmd bus indicates the number of bytes being transferred. The choice of 32- or 64-bit wide system interface dictates whether a cache line block transaction requires 4 double word data cycles or 8 single word cycles, and whether a single datum transfer larger than 4 bytes needs to be broken into two smaller transfers. +DQGVKDNH#6LJQDOV There are six handshake signals on the system interface. Two of these signals, RdRdy* and WrRdy*, are used by an external device to indicate to the RC4650 whether it can accept a new read or write transaction. The RC4650 samples these signals before deasserting the address on read and write requests. ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses between the processor and an external device. When an external device needs to control the interface, it asserts ExtRqst*. The RC4650 responds by asserting Release* to release the system interface to slave state. ValidOut* and ValidIn* are used by the RC4650 and the external device respectively to indicate that there is a valid command or data on the SysAD and SysCmd buses. The RC4650 asserts ValidOut* when it is driving these buses with a valid command or data, and the external device drives ValidIn* when it has control of the buses and is driving a valid command or data. 1RQ02YHUODSSLQJ#6\VWHP#,QWHUIDFH The RC4650 requires a non-overlapping system interface, compatible with the RC4700. This means that only one processor request may
be outstanding at a time and that the request must be serviced by an external device before the RC4650 issues another request. The RC4650 can issue read and write requests to an external device, and an external device can issue read and write requests to the RC4650. The RC4650 asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses. If the system interface has RdRdy* or Read transactions asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting Release*. The external device can then begin sending the data to the RC4650. Figure 4 shows a processor block read request and the external agent read response. The read latency is 4 cycles (ValidOut* to ValidIn*), and the response data pattern is DDxxDD. Figure 5 shows a processor block write. :ULWH#5HLVVXH#DQG#3LSHOLQH#:ULWH The RC4700 and the RC4650 implement additional write protocols designed to improve performance. This implementation doubles the effective write bandwidth. The write re-issue has a high repeat rate of 2 cycles per write. A write issues if WrRdy is asserted 2 cycles earlier and is still asserted at the issue cycle. If it is not still asserted, the last write re-issues again. Pipelined writes have the same 2-cycle per write repeat rate, but can issue one more write after WrRdy de-asserts. They still follow the issue rule as R4x00 mode for other writes. ([WHUQDO#5HTXHVWV The RC4650 responds to requests issued by an external device. The requests can take several forms. An external device may need to supply data in response to an RC4650 read request or it may need to gain control over the system interface bus to access other resources which may be on that bus.
MasterClock SysAD SysCmd ValidOut ValidIn RdRdy WrRdy Release Addr Read Data0 CData Data1 CData Data2 CData Data3 CEOD
Figure 4 RC4650 Block Read Request (64-bit interface option)
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The following is a list of the supported external requests: x Read Response x Null %RRW07LPH#2SWLRQV Fundamental operational modes for the processor are initialized by the boot-time mode control interface. The boot-time mode control interface is a serial interface operating at a very low frequency (MasterClock divided by 256). The low-frequency operation allows the initialization information to be kept in a low-cost EPROM; alternatively the twenty-orso bits could be generated by the system interface ASIC or a simple PAL. To initialize all fundamental, operational modes, immediately after the VCCOK signal is asserted, the processor reads a serial bit stream of 256 bits. After initialization is complete, the processor continues to drive the serial clock output, but no further initialization bits are read. %RRW07LPH#0RGHV The boot-time serial mode stream is defined in Table 5. Bit 0 is the bit presented to the processor when VCCOK is asserted; bit 255 is the last. 3RZHU#0DQDJHPHQW CP0 is also used to control the power management for the RC4650. This is the standby mode and it can be used to reduce the power consumption of the internal core of the CPU. The standby mode is entered by executing the WAIT instruction with the SysAD bus idle and is exited by any interrupt. 6WDQGE\#0RGH#2SHUDWLRQ The RC4650 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This is known as "Standby Mode." (QWHULQJ#6WDQGE\#0RGH Executing the WAIT instruction enables interrupts and enters Standby mode. When the WAIT instruction finishes the W pipe-stage, if the SysAd bus is currently idle, the internal clocks will shut down, thus freezing the pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. If the conditions are not correct when the WAIT instruction finishes the W pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a NOP. Once the CPU is in Standby Mode, any interrupt, including the internally generated timer interrupt, will cause the CPU to exit Standby Mode.
0RGH#ELW 255..15 14..13
'HVFULSWLRQ Must be zero Output driver strength: 10 100% strength (fastest) 11 83% strength 00 67% strength 01 50% strength (slowest) Disable the timer interrupt on Int[5] 0 64-bit system interface 1 32-bit system interface 00 RC4000 compatible 01 reserved 10 pipelined writes 11 write re-issue 0 Little endian 1 Big endian Clock multiplier: 02 13 24 35 46 57 68 7 reserved Writeback data rate: 64-bit 0 1 DDx 2 DDxx 3 DxDx 4 DDxxx 5 DDxxxx 6 DxxDxx 7 DDxxxxxx 8 DxxxDxxx 9-15 reserved Reserved (must be zero) Table 5 Boot-time mode stream 32-bit 0 1 WWx 2 WWxx 3 WxWx 4 WWxxx 5 WWxxxx 6 WxxWxx 7 WWxxxxxx 8 WxxxWxxx 9-15 reserved
11 12 10..9
8 7..5
4..1
0
7KHUPDO#&RQVLGHUDWLRQV
The RC4650 utilizes special packaging techniques to improve the thermal properties of high-speed processors. The RC4650 is packaged using cavity down packaging in a 208-pin QFP (DP). The QFP package allows for an efficient thermal transfer between the die and the case. The R4650 and the RV4650 are guaranteed in a case temperature range of 0C to +85C for commercial temperature parts and in a case temperature range of -40C to +85C for industrial temperature parts. The type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. The equivalent allowable ambient temperature, TA, can be
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calculated using the thermal resistance from case to ambient (CA) of the given package. The following equation relates ambient and case temperatures: TA = TC - P * CA where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for CA at various airflows are shown in Table 6. &$
$LUIORZ#+IW2PLQ, 208 QFP (DP) 3 21 533 13 733 10 933 9 ;33 8 4333 7
&KDQJHV#WR#YHUVLRQ#GDWHG#0DUFK#4<<;= - Added 200 MHz operation frequency. &KDQJHV#WR#YHUVLRQ#GDWHG#$SULO#4<<; Features: - Changed dhrystone/sec reference Power Consumption (RV4650): - Upgraded System Condition Icc active parameters Clock Parameters: - Changed MasterClock period to 200MHz &KDQJHV#WR#YHUVLRQ#GDWHG#)HEUXDU\#4<<< Packaging: - MQUAD packaging changed to PQUAD (DP) &KDQJHV#WR#YHUVLRQ#GDWHG#-XQH#4<<< - Added 267 MHz speed to the RV4650, removed 100MHz from the RV4650 &KDQJHV#WR#YHUVLRQ#GDWHG#-XO\#4<<< - Corrected several incorrect references to figures and tables. &KDQJHV#WR#YHUVLRQ#GDWHG#0DUFK#5333 - Replaced existing figure in Mode Configuration Interface Reset Sequence section with 3 reset figures. - Revised values in System Interface Parameters table.
Table 6 Thermal Resistance (CA) at Various Airflows
Note that the RC4650 implements advanced power management to substantially reduce the average power dissipation of the device. This operation is described in the IDT79RC4640 and IDT79RC4650 RISC Processor Hardware User's Manual.
'DWD#6KHHW#5HYLVLRQ#+LVWRU\
&KDQJHV#WR#YHUVLRQ#GDWHG#6HSWHPEHU#4<<8= AC Electrical Characteristics: - In System Interface Parameters tables (RC4650 and RV4650), Data Setup and Data Hold minimums changed. &KDQJHV#WR#YHUVLRQ#GDWHG#0DUFK#4<<:= Features: - Added 150 MHz operation frequency. - Upgraded spec to "final."
MasterClock
SysAD SysCmd ValidOut ValidIn RdRdy WrRdy Release
Addr Write
Data0 CData
Data1 CData
Data2 CData
Data3 CEOD
Figure 5 RC4650 Block Write Request (64-bit system interface)
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3LQ#'HVFULSWLRQV
The following is a list of interface, interrupt, and miscellaneous pins available on the RC4650. Pins marked with one asterisk are active when low.
####3LQ#1DPH System interface: ExtRqst* Release* RdRdy* WrRdy* ValidIn* Input Output Input Input Input External request Signals that the system interface needs to submit an external request. Release interface Signals that the processor is releasing the system interface to slave state Read Ready Signals that an external agent can now accept a processor read. Write Ready Signals that an external agent can now accept a processor write request. Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. System address/data bus A 64-bit address and data bus for communication between the processor and an external agent. System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. Reserved system command/data identifier bus parity For the RC4650 this signal is unused on input and zero on output. 7\SH 'HVFULSWLRQ
ValidOut*
Output
SysAD(63:0) SysADC(7:0) SysCmd(8:0) SysCmdP
Input/Output Input/Output Input/Output Input/Output
Clock/control interface: MasterClock Input Master clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization. Quiet VCC for PLL Quiet VCC for the internal phase locked loop. Quiet VSS for PLL Quiet VSS for the internal phase locked loop.
VCCP VSSP Interrupt interface: Int*(5:0) NMI*
Input Input
Input Input
Interrupt Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. Non-maskable interrupt Non-maskable interrupt, ORed with bit 6 of the interrupt register.
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IDT79RC4650TM ####3LQ#1DPH Initialization interface: VCCOk Input VCC is OK When asserted, this signal indicates to the RC4650 that the power supply has been above Vcc minimum for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream. Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with MasterClock. Reset This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with MasterClock. Boot mode clock Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. Boot mode data in Serial boot-mode data input. 7\SH 'HVFULSWLRQ
ColdReset*
Input
Reset*
Input
ModeClock ModeIn
Output Input
$EVROXWH#0D[LPXP#5DWLQJV
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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57983 81398( &RPPHUFLDO
597983 61698( &RPPHUFLDO -0.51 to +4.6 0 to +85 -55 to +125 -55 to +125 202 503
597983 61698( ,QGXVWULDO -0.51 to +4.6 -40 to +85 -55 to +125 -55 to +125 202 503
8QLW
VTERM TC TBIAS TSTG IIN IOUT
1.
Terminal Voltage with respect to GND Operating Temperature(case) Case Temperature Under Bias Storage Temperature DC Input Current DC Output Current
-0.51 to +7.0 0 to +85 -55 to +125 -55 to +125 202 503
V C C C mA mA
VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts. 2. When VIN < 0V or VIN > VCC 3. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
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(VCC = 5.05%, TCASE = 0C to +85C)
57983#4330+] 0LQLPXP -- VCC - 0.1V -- 2.4V -0.5V 2.0V -- -- -- -- 0D[LPXP 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 20uA 57983#4660+] 0LQLPXP -- VCC - 0.1V -- 2.4V -0.5V 2.0V -- -- -- -- 0D[LPXP 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 20uA -- -- 0 VIN VCC -- -- Input/Output Leakage |IOUT| = 4mA
3DUDPHWHU VOL VOH VOL VOH VIL VIH IIN CIN COUT I/OLEAK
&RQGLWLRQV |IOUT| = 20uA
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3DUDPHWHU System Condition: ICC standby 57983#4330+] 7\SLFDO4 100/50MHz -- -- active, 64-bit bus option 700 mA2 800 mA2 75 mA2 150 mA2 900 mA2 1000 mA2 0D[ 57983#4660+] 7\SLFDO4 133/67MHz -- -- 900 mA2 1000 mA2 100 mA2 200 mA2 950 mA2 1100 mA2 0D[ -- CL = 0pF3 CL = 50pF CL = 0pF No SysAd activity3 CL = 50pF R4x00 compatible writes, TC = 25oC CL = 50pF Pipelined writes or write reissue, TC = 25oC &RQGLWLRQV
800 mA2
1200 mA4
1000 mA2
1350 mA4
1. 2.
Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25x. These are not tested. They are the results of engineering analysis and are provided for reference only. 3. Guaranteed by design. 4. These are the specifications IDT tests to insure compliance.
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$&#HOHFWULFDO#&KDUDFWHULVWLFV##&RPPHUFLDO#7HPSHUDWXUH#5DQJH57983
(VCC=5.0V 5%; TCASE = -0C to +85C) &ORFN#3DUDPHWHUV57983
57983 4330+] 0LQ Pipeline clock frequency MasterClock HIGH MasterClock LOW MasterClock Frequency1 MasterClock Period Clock Jitter for MasterClock MasterClock Rise Time MasterClock Fall Time ModeClock Period
1. 2.
3DUDPHWHU
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57983 4660+] 0LQ 50 3 3 25 15 -- -- -- -- 0D[ 133 -- -- 67 40 250 4 4 256* tMCP
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2
50 4 4 25 20 -- -- -- --
MHz ns ns MHz ns ps ns ns ns
tMCP tJitterIn2 tMCRise tMCFall
2 2
-- -- --
tModeCKP
Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled. Guaranteed by design.
6\VWHP#,QWHUIDFH#3DUDPHWHUV57983
(VCC=5.0V 5%; TCASE = 0C to +85C) Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
57983 4330+] 0LQ Data Output1 tDO = Max mode14..13 = 10 (fastest) mode14..13 = 11 (85%) mode14..13 = 00 (66%) mode14..13 = 01 (slowest) Data Output Hold tDOH3 mode14..13 = 10 mode14..13 = 11 mode14..13 = 00 mode14..13 = 01 Data Setup Data Hold
1.
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trise = 5ns tfall = 5ns
5.5 2
-- --
4.5 1.5
-- --
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Capacitive load for all output timings is 50pF. 2. Guaranteed by design. 3. 50pf loading on external output signals, fastest settings
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(VCC=5.0V 5%; TCASE = 0C to +85C)
57983 4330+] 0LQ 3 0 0D[ -- -- 57983 4660+] 0LQ 3 0 0D[ -- -- Master Clock Cycle Master Clock Cycle
3DUDPHWHU
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7HVW# &RQGLWLRQV -- 4330+] 0LQ -- 0D[ 2 4660+] 0LQ -- 0D[ 2
3DUDPHWHU Load Derate
6\PERO CLD
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'&#(OHFWULFDO#&KDUDFWHULVWLFV##&RPPHUFLDO#2#,QGXVWULDO#7HPSHUDWXUH# 5DQJH597983
(VCC = 3.35%, Commercial TCASE = 0C to +85C, Industrial TCASE = -40C to +85C)
597983#4660+] 0LQLPXP -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- -- 0D[LPXP 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 20uA 597983#4830+] 0LQLPXP -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- -- 0D[LPXP 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 20uA -- -- 0 VIN VCC -- -- Input/Output Leakage |IOUT| = 4mA
3DUDPHWHU VOL VOH VOL VOH VIL VIH IIN CIN COUT I/OLEAK
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3DUDPHWHU VOL VOH VOL VOH VIL
597983#4;30+]
597983#5330+]
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0LQLPXP 0D[LPXP 0LQLPXP 0D[LPXP 0LQLPXP 0D[LPXP -- VCC - 0.1V -- 2.4V -0.5V 0.1V -- 0.4V -- 0.2VCC -- VCC - 0.1V -- 2.4V -0.5V 0.1V -- 0.4V -- 0.2VCC -- VCC - 0.1V -- 2.4V -0.5V 0.1V -- 0.4V -- 0.2VCC --
&RQGLWLRQV |IOUT| = 20uA
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1.
0LQLPXP 0D[LPXP 0LQLPXP 0D[LPXP 0LQLPXP 0D[LPXP 0.7VCC -- -- -- -- VCC + 0.5V 10uA 10pF 10pF 20uA 0.7VCC -- -- -- -- VCC + 0.5V 10uA 10pF 10pF 20uA 0.7VCC -- -- -- -- VCC + 0.5V 10uA 10pF 10pF 20uA --
&RQGLWLRQV
0 VIN VCC -- -- Input/Output Leakage
Industrial temperature range is not available at 267MHz
3RZHU#&RQVXPSWLRQ597983
3DUDPHWHU System Condition ICC standby 597983#4660+] 7\SLFDO4 133/67MHz -- -- active, 64-bit bus option 625 mA2 700 mA2 60 mA2 110 mA2 700 mA2 800 mA2 0D[ 597983#483#0+] 7\SLFDO4 150/75MHz -- -- 700 mA2 850mA2 60mA2 110mA2 800mA2 900mA2 0D[ -- CL = 0pF3 CL = 50pF CL = 0pF, No SysAd activity3 CL = 50pF R4x00 |compatible writes TC = 25oC 700 mA2
1. 2.
&RQGLWLRQV
900 mA4
850mA2
1000mA4
CL = 50pF Pipelined writes or Write re-issue, TC = 25oC
Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25x. These are not tested. They are the result of engineering analysis and are provided for reference only. 3. Guaranteed by design. 4. These are the specifications IDT tests to insure compliance.
3DUDPHWHU
597983#4;3#0+] 597983#533#0+] 7\SLFDO4 0D[ 7\SLFDO4 200/100MHz 60mA2 110mA2 900mA2 1000mA2 1200mA4 -- -- 925mA2 1000mA2 1000mA2 60mA2 110mA2 1000mA2 1100mA2 1300mA4 0D[
597983#59:#0+] 7\SLFDO4 267/89MHz -- -- 925mA2 1000mA2 1000mA2 60mA2 110mA2 1100mA2 1300mAb 1500mAa 0D[ --
&RQGLWLRQV
System Condition 180/90MHz ICC standby -- -- active, 64-bit bus option 855 mA2 930mA2 930mA2
1. 2.
CL = 0pF3 CL = 50pF CL = 0pF, No SysAd activity3 CL = 50pF R4xxx|compatible writes TC = 25oC CL = 50pF Pipelined writes or Write re-issue, TC = 25oC
Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25x. These are not tested. They are the result of engineering analysis and are provided for reference only. 3. Guaranteed by design. 4. These are the specifications IDT tests to insure compliance.
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(VCC=3.3V 5%; Commercial TCASE = 0C to +85C, Industrial TCASE = -40C to +85C) &ORFN#3DUDPHWHUV597983 Note: Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
597983 4660+] 0LQ Pipeline clock Frequency MasterClock HIGH MasterClock LOW MasterClock Frequency1 MasterClock Period Clock Jitter for MasterClock MasterClock Rise Time MasterClock Fall Time ModeClock Period
1. 2.
3DUDPHWHU
6\PERO
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8QLWV
0D[ 133 -- -- 67 40 250 4 4 256* tMCP MHz ns ns MHz ns ps ns ns ns
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--
50 Transition tMCRise/Fall Transition tMCRise/Fall -- -- --
2
3 3 25 15 -- -- -- --
tMCP tJitterIn2 tMCRise tMCFall2 tModeCKP2
-- -- --
Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
3DUDPHWHU
597983 4830+] 0LQ 0D[ 150 -- -- 75 40 250 3 3 256* tMCP
597983 4;30+] 0LQ 50 3 3 25 11.1 -- -- -- -- 0D[ 180 -- -- 90 40 250 2.5 2.5 256* tMCP
597983 5330+] 0LQ 50 3 3 25 10 -- -- -- -- 0D[ 200 -- -- 100 40 250 2 2 256* tMCP
597983 59:0+] 0LQ 100 3 3 50 8 -- -- -- -- 0D[ 267 -- -- 125 20 250 2 2 256* tMCP
8QLWV
Pipeline clock Frequency MasterClock HIGH MasterClock LOW MasterClock Frequency MasterClock Period Clock Jitter for MasterClock MasterClock Rise Time MasterClock Fall Time ModeClock Period
(5)
50 3 3 25 13.3 -- -- -- --
MHz ns ns MHz ns ps ns ns ns
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(VCC=3.3V 5%; Commercial TCASE = 0C to +85C, Industrial TCASE = -40C to +85C) Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
597983 46629:0+] 0LQ Data Output1 tDM= Min tDO = Max tDOH2 tDS tDH mode14..13 = 10 (fastest) mode14..13 = 01 (slowest) mode14..13 = 10 (fastest) trise = 5ns tfall = 5ns 1.0 2.0 1.0 4.5 1.5 0D[ 9 12 -- -- -- 597983 4832:80+] 0LQ 1.0 2.0 1.0 4.5 1.5 0D[ 9 12 -- -- -- ns ns ns ns ns
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Data Output Hold Input Data Setup Input Data Hold
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Capacitive load for all output timings is 50pF. 50pf loading on external output signals, fastest settings
3DUDPHWHU
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597983 4;32 <30+] 0LQ 0D[ 9 10 -- -- --
597983 5332 4330+] 0LQ 1.0 2.0 1.0 4.5 1.5 0D[ 4.5 5.0 -- -- --
597983 59:2;<0+] 0LQ 1.0 -- 1.0 2.5 1.0 0D[ 4.5 5.0 -- -- --
8QLWV
Data Output
tDM= Min tDO = Max tDOH* tDS tDH
mode14..13 = 10 (fastest) mode14..13 = 01 (slowest) mode14..13 = 10 (fastest) trise = 3ns tfall = 3ns
1.0 2.0 1.0 4.5 1.5
ns ns ns ns ns
Data Output Hold Data Input
50pf loading on external output signals, fastest settings
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3DUDPHWHU
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Mode Data Setup Mode Data Hold
tDS tDH
ns ns
Master Clock Cycle Master Clock Cycle
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3DUDPHWHU Load Derate
6\PERO CLD
8QLWV ns/25pF
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7LPLQJ#&KDUDFWHULVWLFV597983
Cycle M asterClock t MCkHigh tMCkLow tMCkP 1 2 3 4
SysAD,SysCm d Driven SysADC
D t DM tDO
D tDOH
D tDZ
SysAD,SysCm d Received SysADC
D t DS tDH
D
D
D
Control Signal CPU driven ValidOut* Release* Control Signal CPU received RdRdy* W rRdy* ExtRqst* ValidIn* NM I* Int*(5:0)
* = active low signal
tDO tDOH
tDS
tDH
Figure 6 System Clocks Data Setup, Output, and Hold timing
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0RGH#&RQILJXUDWLRQ#,QWHUIDFH#5HVHW#6HTXHQFH
Vcc
MasterClock
2.3V 2.3V
(MClk)
TDS > 100ms 256 MClk cycles 256 MClk cycles
VCCOK
ModeClock TMDS TMDH Bit 0 TDS ColdReset* TDS > 64K MClk cycles > 64 MClk cycles TDS Bit 1 Bit 255 TDS
ModeIn
Reset*
Figure 7 Power-on Reset
Vcc
Master Clock
(MClk)
VCCOK
TDS > 100ms
TDS 256 MClk cycles 256 MClk cycles
ModeClock
TMDS Bit 0 TDS TMDH Bit Bit 1 255 TDS > 64K MClk cycles > 64 MClk cycles TDS TDS
ModeIn
ColdReset*
Reset*
Figure 8 Cold Reset
Vcc
Master Clock
(MClk)
VCCOK 256 MClk cycles
ModeClock
ModeIn
ColdReset* TDS TDS > 64 MClk cycles
Reset*
Figure 9 Warm Reset
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Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
3LQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 )XQFWLRQ N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD11 VSS VCC SysCmd8 SysAD42 SysAD10 SysCmd7 VSS VCC SysAD41 SysAD9 SysCmd6 SysAD40 VSS VCC SysAD8 SysCmd5 SysADC4 SysADC0 VSS VCC SysCmd4 SysAD39 SysAD7 SysCmd3 VSS 3LQ 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 )XQFWLRQ N.C. N.C. N.C. N.C. SysCmd2 SysAD36 SysAD4 SysCmd1 VSS VCC SysAD35 SysAD3 SysCmd0 SysAD34 VSS VCC SysAD2 Int51 SysAD33 SysAD1 VSS VCC Int41 SysAD32 SysAD0 Int31 VSS VCC Int21 SysAD16 SysAD48 Int11 VSS VCC SysAD17 3LQ 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 )XQFWLRQ N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD52 ExtRqst1 VCC VSS SysAD21 SysAD53 RdRdy1 Modein SysAD22 SysAD54 VCC VSS Release1 SysAD23 SysAD55 NMI1 VCC VSS SysADC2 SysADC6 SysAD24 VCC VSS SysAD56 SysAD25 SysAD57 3LQ 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 )XQFWLRQ N.C. N.C. SysAD59 ColdReset1 SysAD28 VCC VSS SysAD60 Reset1 SysAD29 SysAD61 SysAD30 VCC VSS SysAD62 SysAD31 SysAD63 VCC VSS VCCOK SysADC3 SysADC7 N.C. N.C. N.C. N.C. N.C. N.C. VCCP VSSP MasterClock VCC VSS SysADC5 SysADC1
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N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
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IDT79RC4650TM
IDT79
YY Operating Voltage
XXXX Device Type
999 Speed
A Package
A Temp range/ Process
Blank I
Commercial (0C to +85C Case) Industrial (-40C to +85C Case)
DP 100 133 150 180 200 267
208-pin QFP 100 MHz 133 MHz 150 MHz 180 MHz 200 MHz 267 M Hz 64-bit processor w/ DSP Capability 5.0+/-5% 3.3+/-5%
4650
R RV
9DOLG#&RPELQDWLRQV#
IDT79R4650 - 100, 133MHz DP IDT79RV4650 - 133, 150, 180, 200, 267MHz DP IDT79RV4650 - 133, 150, 180, 200MHz DPI QFP package, Commercial Temperature QFP package, Commercial Temperature QFP package, Industrial Temperature
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: email: rischelp@idt.com phone: 408-492-8208
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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